Author: Kai Skibbe
Date: 06:00:23 10/22/98
Go up one level in this thread
On October 22, 1998 at 08:17:59, Robert Hyatt wrote: >On October 22, 1998 at 01:12:46, Kai Skibbe wrote: > >>On October 21, 1998 at 11:08:15, James Robertson wrote: >> >>>On October 21, 1998 at 10:54:16, James T. Walker wrote: >>> >>>>If I understood a previous thread, Dr. Hyatt indicated that there is >effectively >>>>no move ordering done by most programs(At least Crafty)? >>> >>>Crafty orderes moves by firstly trying the hash move, then killers? (I'm not >>>sure), then gainful captures, etc. There is actually a lot of move ordering >>>done, but for Crafty, it is all in *generating* more promising moves first. My >>>program has very primitive move ordering, using only pv search, gainful >>>captures, and killer moves. Each one of these heuristics has reduced move time >>>by 25% to 50%, so obviously move ordering is really important. I plan to add >>>hash, history (this will profoundly rearrange your move list), and other stuff >>>as soon as I find out I failed biology, and say "the heck with it. Might as well >>>work on my program!" :) >>> >>>>Can anyone please >>>>answer this for me?? It seems unreal that there would be no attempt to order >>>>the moves so that the most promising moves were searched first. >>>> >>>>Another question-- Can anyone tell me if there is any advantage to having 1 meg >>>>of L2 cache vs 512K relative to chess programs? >> >>Hi Jim, >> >>the speed difference will be minimal, but with most motherboards the cacheable >>area with 1MB L2Cache is twice as with 512KCache. So I think 1M L2 Cache is >>worth the extra money. >>For example I have the NMC 5VMMX with 1MB Cache and the cacheable area is 256MB >>RAM. With only 512KB Cache the cacheable area would be only 128MB RAM. >> >> >>Best Regards >>Kai >> > > > > > > > > > > >This isn't always true. IE the PII's (anything 300mhz and up at least) >can cache the full 32 gigs of main memory, if you can afford it. The >size of cache should have no effect on how much memory can be cached. It >depends on the design of the cache and the size of the tag ram used for >verifying cache hits. > >However, I haven't seen any designs where doubling cache doubles the amount >of cacheable RAM... because the size of the cache is usually a jumper on >motherboards. There were some few pentiums and pentium II's that could >only cache the first 64MB... but for any pentium II, external cache >doesn't exist, so we are talking about regular pentiums or clones I assume, >since the pro's and II's have the L2 cache internal... Hi Bob, I think you are right with intel pentium II chips. But my motherboard has a Socket 7 and the available processors for this socket doesn´t have the L2-cache inside. With 1MB L2-Cache my motherboard has a chacheable area of 256MB RAM. You can´t change the tag ram to increase the cacheable area. I think that doubling the cache size has the same affect of doubling the cacheable area to all motherboard with the VIA-chipset. Other none Intel-chipsets may have the same affect. Another influence of the cacheable area is the cache strategy. I think with "write back" the cacheable area is half (128MB) as with "write through" (256MB). Best regards Kai > >> >>> >>>I haven't a clue! >>> >>>>Thanks,\ >>>>Jim Walker >>> >>>Hope I helped, >>>James
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