Author: Dan Andersson
Date: 19:19:22 06/23/03
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Ars Technica has an article on the 970. They mention a few things. No on die memory controller. That gives higher latency. Weaker AltiVec implementation. The FSB is said to be 1/4 of clock speed. No one knows if that is going to hold true. And address and control information is multiplexed in to that stream. That makes a DDR bus a good fit. But also makes us realize that the real world bandwidth will be worse. I would love to test a system and see what its characteristics are. MvH Dan Andersson
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