Author: Eugene Nalimov
Date: 15:50:49 07/01/03
Go up one level in this thread
On July 01, 2003 at 18:12:17, Robert Hyatt wrote: >On July 01, 2003 at 16:45:20, Tom Kerrigan wrote: > >>On July 01, 2003 at 16:02:40, Robert Hyatt wrote: >> >>>On July 01, 2003 at 13:20:32, Tom Kerrigan wrote: >>> >>>>On July 01, 2003 at 11:57:58, Robert Hyatt wrote: >>>> >>>>>On June 30, 2003 at 21:03:30, Tom Kerrigan wrote: >>>>> >>>>>>On June 29, 2003 at 23:50:11, Robert Hyatt wrote: >>>>>> >>>>>>>On June 29, 2003 at 06:35:02, Tony Werten wrote: >>>>>>> >>>>>>>>On June 28, 2003 at 14:23:50, Robert Hyatt wrote: >>>>>>>> >>>>>>>>>On June 28, 2003 at 12:12:15, Jay Urbanski wrote: >>>>>>>>> >>>>>>>>>>On June 28, 2003 at 10:33:45, Robert Hyatt wrote: >>>>>>>>>> >>>>>>>>>>>Those are not true 64 bit processors. Supposedly 32 bit stuff runs just >>>>>>>>>>>fine on them, but they have 64 bit extensions. >>>>>>>>>> >>>>>>>>>>How is Opteron not a true 64-bit processor? >>>>>>>>> >>>>>>>>> >>>>>>>>>Because it executes 32 bit instructions _also_. >>>>>>>> >>>>>>>>P4 and AMD also execute 16-bit instructions, so they are 16 bit processors ? >>>>>>> >>>>>>>Not pure 16 bit no. Not pure 32 either. >>>>>>> >>>>>>>Check out "Cray" for a better example of a pure architecture. >>>>>>> >>>>>>>All math is 64 bits. All address arithmetic is 32 bits. Different >>>>>>>instructions, functional units, and registers for each. No kludges about >>>>>>>gating 32 bits with 32 high-end zeroes and that kind of stuff. >>>>>>> >>>>>>>But in the case of opteron, at least at first look, it appears to be a 32 >>>>>>>bit machine with 64 bit instructions layered on top. >>>>>> >>>>>>Are you kidding me? >>>>>> >>>>>>The "bitiness" is the width of a chip's datapath, right? >>>>> >>>>>Yes. But there is more. A chip made to do 64 bit operations as its _normal_ >>>>>mode of functioning is a 64 bit chip. A chip that does 32 bit operations >>>>>normally, with 64 bit add-ons, is not really a _full_ 64 bit chip. >>>>> >>>>>That was, and is, my point. >>>> >>>>How do you figure that the Opteron/PA-RISC/UltraSPARC/MIPS/POWER do not do >>>>64-bit operations as their "normal" mode of functioning? They have 64 bit >>>>registers and the values in those registers are communicated over 64 bit busses >>>>to 64 bit buffers and 64 bit latches and 64 bit ALUs. How can you possibly get >>>>more 64 bit than that? Just because all of this hardware _can_ be utilized to >>>>also execute 32 bit instructions (the same way a chip does a "2 bit instruction" >>>>when you calculate the sum of 1 + 1) doesn't mean it's not a 64 bit chip. >>> >>>No, but it _very likely_ means that the design has some trade-offs to make the >>>32 bit stuff work. IE it is simply easier to do everything in 64 bit mode >>>rather than having to special-case some 32 bit stuff using the same registers, >>>as then there are all the normal sign-bit problems, to name just one issue. >> >>Yes, there are some sign issues and some flag bit issues but if you know >>anything about logic design you know those are insignificant. Alpha is a pure 64 >>bit chip and it still has to do sign extension stuff for when you load 8, 16, or >>32 bit values and want them sign-extended. So you can reuse logic that's already >>there. I refuse to believe that 32 bit support in any of these chips involves >>trade-offs in any way. >> >>>>>It runs X86 natively. That is a 32 bit instruction set. >>>> >>>>So does IA64, although you apparently didn't realize this. >>> >>>No I didn't, although I am not an IA64 person. However, how does a VLIW >>>architecture execute mov al,x type instructions? If the hardware can do >>>that it would be interesting. If software has to do some translation then >> >>The same way a RISC architecture (e.g., Pentium 4) executes mov al,x type >>instrcutions. >> >>-Tom > > >The problem is, the X86 architecture _defines_ mov al,x. But I don't see >that in the VLIW definition for Itanium... Not that I intend to be an >Itanium assembly programmer any time soon unless we get a few and they are >available for chess. :) IA-64 Processor Programmers Reference. Manual Vol. 4 -- IA-32 Instruction Set Description. I have it on the desk near me. Also, you can find lot of stuff in the vol. 1 through 3. How IA-32 registers are mapped into IA-64 registers, how 32-bit code can interoperate with 64-bit one, how interrupts and traps are handled when CPU is in the 32-bit mode, etc. Open those books and enjoy :-) Thanks, Eugene
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