Author: Tom Kerrigan
Date: 18:15:35 07/01/03
Go up one level in this thread
On July 01, 2003 at 20:29:58, Robert Hyatt wrote: >>Really? Which RISC computers don't use 32 bit instructions? POWER, Alpha, SPARC, >>PA-RISC, MIPS, ARM, and probably some others I'm forgetting all use 32 bit >>instructions. > >Look again. IE addresses stretch the instruction way beyond 32 bits for >those instructions that need addresses. The sparc is an easy to find >example of this. IE the 32 bit sparc had instructions > 32 bits. Really? Which ones? >>ARM has a 16 bit instruction format to increase code density. I >>suppose Itanic uses 40 bits per instruction... rare exception... >> >>How do 32 bits limit the # of registers? A 3 operand instruction with an 8 bit >>opcode can use 8 bits per register = 256 registers. > >Simple. You end up with multiple things to fit in the instruction. Opcode >which can be 8 bits and up. Registers (sometimes three, sometimes more >depending on the machine. IE destination, two sources + an index or a >displacement plus an index, etc. I can't think of a single case where an >architect said "ok, this is enough bits, there is nowhere I would wish for >another couple of bits." That's where the current X86 problems came from, >in fact. On the sparc you need 15 bits for the three operands, plus more >for the opcode and displacement. What x86 problems? The x86 has variable length instructions anyway, so you can't say that n-bit-long instructions limit it somehow. >As to your specific question, 32 bits _could_ be set up for 8 bits for >the opcode, and 8 bits for three registers. But then how do you add 2 >to a register? How do you even get 2 into a register other than loading >it from memory? The immediate values are useful, but they are too small >on the sparc in many cases. Has it really been so long since you studied computer architecture that you've forgotten everything? What RISC architecture requires 3 operands for add immediate and load immediate instructions? Even with 8 bit opcodes and 8 bit register fields, you can still add 8 bit immediate values (16 bit if you write it back to the same register) and load 16 bit immediate values. add r1, r2, 0xFF load r1, 0xFFFF >Now, for IA-64. An instruction is 128 bits long (an instruction bundle). >This contains _three_ 41 bit instructions plus the 5 bit template. That's >not exactly 32 bits, so there is another example of non-32bit instruction Right, I already said that in my last post. What was it you always tell me about reading comprehension? -Tom
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