Author: Robert Hyatt
Date: 11:27:19 07/02/03
Go up one level in this thread
On July 02, 2003 at 00:02:57, Tom Kerrigan wrote: >On July 01, 2003 at 22:19:38, Eugene Nalimov wrote: > >>On July 01, 2003 at 21:15:35, Tom Kerrigan wrote: >> >>>On July 01, 2003 at 20:29:58, Robert Hyatt wrote: >>> >>>>>Really? Which RISC computers don't use 32 bit instructions? POWER, Alpha, SPARC, >>>>>PA-RISC, MIPS, ARM, and probably some others I'm forgetting all use 32 bit >>>>>instructions. >>>> >>>>Look again. IE addresses stretch the instruction way beyond 32 bits for >>>>those instructions that need addresses. The sparc is an easy to find >>>>example of this. IE the 32 bit sparc had instructions > 32 bits. >>> >>>Really? Which ones? >> >>"Load high" is a kludge added to the instruction set of nearly every recent RISC >>CPU to resolve exactly that problem -- "how we can load 32-bit value when all >>the instructions are 32 bits in length"? Conceptually, "load high/add immediate" >>is one instruction. > >Oh, God. I knew that one of these ISAs allowed a 32-bit immediate following the >instruction. I didn't think most of them did. That violates the RISC philosophy >in so many ways. > >I thought most of these ISAs just had a 2nd load immediate instruction that >loaded the immediate operand into the upper order bits of a register? > >Takes two instructions to load a 32 bit value into a register, but it's not like >the program's memory footprint is any bigger, and it's not like you have to load >such big values into registers very often... > >-Tom Unless you are writing a chess program. :) But the sparc needs two instructions to load a 32 bit value. Extrapolate for 64 bit immediate values. :) Of course you don't do them. You do a 64 bit load from memory. And whether that is good or bad is debatable when compared to a variable-length instruction. The issue becomes speed, and avoiding a memory reference is a good thing. And avoiding a decode quagmire is a good thing. So this point is "open" for debate.
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