Author: Tom Kerrigan
Date: 16:29:45 07/02/03
Go up one level in this thread
On July 02, 2003 at 14:24:28, Robert Hyatt wrote: >On July 01, 2003 at 21:15:35, Tom Kerrigan wrote: > >>On July 01, 2003 at 20:29:58, Robert Hyatt wrote: >> >>>>Really? Which RISC computers don't use 32 bit instructions? POWER, Alpha, SPARC, >>>>PA-RISC, MIPS, ARM, and probably some others I'm forgetting all use 32 bit >>>>instructions. >>> >>>Look again. IE addresses stretch the instruction way beyond 32 bits for >>>those instructions that need addresses. The sparc is an easy to find >>>example of this. IE the 32 bit sparc had instructions > 32 bits. >> >>Really? Which ones? > >Actually that was vague and I was wrong. On the sparc, it simply takes >two instructions to load big values. On the Cray and Vax, among others, >the instructions "stretch out". Right, fixed-length instructions were a cornerstone of the RISC philosophy, so it's no big surprise that pre-RISC ISAs in general have variable length instructions. >>What x86 problems? The x86 has variable length instructions anyway, so you can't >>say that n-bit-long instructions limit it somehow. > >Sure I can. It first limits the number of registers to 3 bits. I'd bet >that if Intel could "start over" the ISA would be greatly different with a >target of 32 bits from the beginning. Intel grew up from 8 bits. Other >vendors started at 32 and their instruction sets are _far_ better. Motorolla >is an example with the 680x0. The sparc has a nice instruction set, it's just >a dog for performance. I don't know what in the world you're talking about. Grew up from 8 bits? Target 32 bits? Started at 32 bits? Do you know what "variable length instructions" means? x86/680x0 didn't start at, target, or grow up from ANY length. >>Has it really been so long since you studied computer architecture that you've >>forgotten everything? What RISC architecture requires 3 operands for add >>immediate and load immediate instructions? Even with 8 bit opcodes and 8 bit >>register fields, you can still add 8 bit immediate values (16 bit if you write >>it back to the same register) and load 16 bit immediate values. > >Perhaps _none_ require it. After all the original sparc didn't implement >integer multiply/divide in hardware. But they quickly added it when the >performance metrics were run. > >But I can think of _several_ reasons for 3 registers + an immediate value. Okay, okay, I give up. OF COURSE 32 bit instructions limit the number of registers you can have. You can't have 5 billion registers, for example. I don't even know why we're arguing about this. All I did was say that RISC instructions are 32 bits regardless of whether the chip is 32 or 64 bits. I don't want to argue about whether or not 32 bit instructions are actually good or not. I'll consider my point made, let's move on already. -Tom
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