Author: Keith Evans
Date: 18:02:50 07/02/03
Go up one level in this thread
> >If it's already choosing between 3 bits with one gate delay, it can choose >between 4 bits with one gate delay. Also I think that the custom designs (not standard cell or gate array) do a lot of transistor level design when necessary. You can do some clever tricks this way. I'm pretty sure that this is common for ALUs.
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