Author: Tom Kerrigan
Date: 18:35:44 07/02/03
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On July 02, 2003 at 21:02:50, Keith Evans wrote: > >> >>If it's already choosing between 3 bits with one gate delay, it can choose >>between 4 bits with one gate delay. > >Also I think that the custom designs (not standard cell or gate array) do a lot >of transistor level design when necessary. You can do some clever tricks this >way. I'm pretty sure that this is common for ALUs. Indeed, it's very low level for the core. One of the supposed advantages of POWER4 is that it's higher level, maybe a lot of it is in an HDL? That's why they were able to bring it to market so quickly and why they can port it to new processes so quickly. -Tom
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