Author: Tom Kerrigan
Date: 18:56:35 07/02/03
Go up one level in this thread
On July 02, 2003 at 01:13:25, Eugene Nalimov wrote: >On July 02, 2003 at 00:02:57, Tom Kerrigan wrote: > >>On July 01, 2003 at 22:19:38, Eugene Nalimov wrote: >> >>>On July 01, 2003 at 21:15:35, Tom Kerrigan wrote: >>> >>>>On July 01, 2003 at 20:29:58, Robert Hyatt wrote: >>>> >>>>>>Really? Which RISC computers don't use 32 bit instructions? POWER, Alpha, SPARC, >>>>>>PA-RISC, MIPS, ARM, and probably some others I'm forgetting all use 32 bit >>>>>>instructions. >>>>> >>>>>Look again. IE addresses stretch the instruction way beyond 32 bits for >>>>>those instructions that need addresses. The sparc is an easy to find >>>>>example of this. IE the 32 bit sparc had instructions > 32 bits. >>>> >>>>Really? Which ones? >>> >>>"Load high" is a kludge added to the instruction set of nearly every recent RISC >>>CPU to resolve exactly that problem -- "how we can load 32-bit value when all >>>the instructions are 32 bits in length"? Conceptually, "load high/add immediate" >>>is one instruction. >> >>Oh, God. I knew that one of these ISAs allowed a 32-bit immediate following the >>instruction. I didn't think most of them did. That violates the RISC philosophy >>in so many ways. >> >>I thought most of these ISAs just had a 2nd load immediate instruction that >>loaded the immediate operand into the upper order bits of a register? > >Sorry, I was not clear enough. I was talking about exactly those two >instructions. RISC developers ended with 2 instructions instead of one because >of the limitation "all instruction should have the same length". That is what >Bob was talking about -- sometimes you need more than 32 bits to encode the >instruction. Of course you can split instruction into two. You can implement >"prefix instruction". You can invent instruction that will use some bits of the >next instruction as operand bits. That are all kludges. I don't see the load/load-high instruction pair as a kludge (or one instruction) at all. RISC instructions operate on registers. Loading high bits seems like a completely legitimate, unique operation to me. It's not written in stone anywhere that loading an entire register with an immediate has to or should be done with one instruction. In fact, I've never heard anybody discuss it as a kludge until now. >RISC code is longer than it should be, mainly because of that limitation. You >yourself pointed out that for majority of instructions 32 bits are too much. >Nevertheless, "all instructions should have the same length", and due to the >fact that you need longer immediate operands (or offsets) instructions cannot be >short, even ones that do not require those extra bits. > >I personally think that ARM choose right way in their Thumb2 instruction set. >You need a mixture of 16- and 32-bit instructions (probably with 48-bit >instructions as well), and instruction length should be easily deduciable from >the first instruction word. This way you can have both fast instruction >fetch/decode and compact code. I think this would still make fetch/decode annoyingly difficult. The Athlon L1 i-cache has to have extra logic to keep track of where instructions start. Another benefit of having equal length instructions is that you effectively get a few extra bits for your immediate offset for branches. Is code size really that big an issue? L1 instruction caches have absurdly high hit rates, and if the code gets bloated, you can just increase the cache size to maintain that hit rate... -Tom
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