Author: Robert Hyatt
Date: 13:22:11 10/26/98
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On October 26, 1998 at 10:59:14, James Robertson wrote: >On October 25, 1998 at 13:28:05, Robert Hyatt wrote: > >[....] > >>> >>>I still have problems understanding. Suppose you have, starting at address 0, >>>four 8-bit values. If you access the first, then the whole "clump" of 32 bytes >>>are loaded into the L2 cache. Ok, that makes sense. >>> >>>Suppose you access the second byte in chunk 0. Does the computer load chunk 0 >>>(bytes 0-3) into memory? or does it load bytes 1-4 into memory? Thanks for the >>>help! >>> >>>James >>> >> >>cache lines are *always* aligned on 32 byte boundaries... so if you access >>*any* byte between 0 and 31, all the bytes in the line get loaded from bytes >>0-31 in memory... non-boundary aligned caches were done many years ago, but >>cause problems with todays 32 bit "banks"... >> > >Ok, this clears up one problem I got from not reading enough of the previous >messages in this thread.... the cache is 32 bytes long, not 32 bits. Suppose you >have an array, say, of 50 3-bit structures. Obviously 32 is not divisible by 3, >so will the machine "split" a structure between two lines? Obviously this is >necessary for huge structures, but are smaller treated differently? > >James None of that has anything to do with cache... just think of memory as being broken up into 32 byte "lines" rather than 4 byte words... a reference to any byte in a single line results in the entire line being loaded into cache. If the part of the "thing" you reference is in line X, then line X is popped into cache in its entirety. If it is longer than a single line, doesn't matter, because lines are fetched as bytes within a line are accessed... So the cpu only sees memory-to-cache-line mapping. How the compiler did the structure-to-memory mapping is unimportant to the hardware, because the hardware doesn't understand *anything* about "structures" and such... those are compiler abstractions of the basic memory model...
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