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Subject: Re: Source code to measure it - there is something wrong

Author: Robert Hyatt

Date: 20:37:53 07/15/03

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On July 15, 2003 at 20:30:04, Vincent Diepeveen wrote:

>On July 15, 2003 at 20:08:57, Robert Hyatt wrote:
>
>>On July 15, 2003 at 17:58:01, Gerd Isenberg wrote:
>>
>>>Ok, i think there is one problem with Vincent's cache benchmark.
>>>
>>>There are two similar functions DoNrng and DoNreads. DoNrng is used to mesure
>>>the time without hashread. But the instructions has the potential of faster
>>>execution due to less dependencies and stalls. It may execute parts of two loop
>>>bodies of DoNrng interlaced or simultaniesly - that is not possible in DoNreads.
>>>Therefore the time for N DoNrng is not the time used inside the N DoNrng loop,
>>>and maybe much faster.
>>
>>That is also certainly possible.  This kind of "problem" is highly
>>obfuscated, as you can see.  It requires a lot of analysis, by a lot of
>>people, to see the flaws.  That's why lm-bench is so respected.  It was
>>written, a paper was written about it, another paper was written that
>>pointed out some flaws, some of which were fixed and some of which were
>>not really flaws.  But it has been pretty well looked at by a _lot_ of
>>people.
>>
>>Other latency measures may well be as accurate, but until they "pass the
>>test of time and exposure" they are hard to trust.
>
>For sure my test shows that it isn't 130 ns. It's more like 280 ns for 133Mhz
>DDR ram. not sure whether you got RDRAM in your machine or 100Mhz DDR ram. but
>you for sure aren't at 130ns random memory latency there.

I have told you this a dozen times.  I have 100mhz quad pumped (400mhz)
DDR RAM.  lm_bench reports 150ns latency.

End of story.


>
>If instructions get paired better or worse is not real interesting. It is nice
>when it measures in 0.1 ns accurate but if it is an error of 0.5 ns like it is
>now (assuming no other software is disturbing) then that is not a problem for me
>knowing the actual latencies lie in 210 for 150Mhz ram (just 300MB cache which
>is definitely too little) to 280 for 133Mhz ram (with 500MB cache) at P4 to
>nearly 400 ns for dual P4/K7s with DDR ram 133Mhz.
>
>>>
>>>
>>>int DoNrng(BITBOARD n) {
>>>  BITBOARD i=1,dummyres,nents;
>>>  int t1,t2;
>>>
>>>  nents = nentries; /* hopefully this gets into a register */
>>>  dummyres = globaldummy;
>>>
>>>  t1 = GetClock();
>>>  do {
>>>    BITBOARD index = RanrotA()%nents;
>>>    dummyres ^= index;
>>>  } while( i++ < n );
>>>  t2 = GetClock();
>>>
>>>  globaldummy = dummyres;
>>>  return(t2-t1);
>>>}
>>>
>>>int DoNreads(BITBOARD n) {
>>>  BITBOARD i=1,dummyres,nents;
>>>  int t1,t2;
>>>
>>>  nents = nentries; /* hopefully this gets into a register */
>>>  dummyres = globaldummy;
>>>
>>>  t1 = GetClock();
>>>  do {
>>>    BITBOARD index = RanrotA()%nents;
>>>    dummyres ^= hashtable[index];
>>>  } while( i++ < n );
>>>  t2 = GetClock();
>>>
>>>  globaldummy = dummyres;
>>>
>>>  return(t2-t1);
>>>}



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