Computer Chess Club Archives


Search

Terms

Messages

Subject: Re: Source code to measure it - there is something wrong

Author: Gerd Isenberg

Date: 23:17:29 07/16/03

Go up one level in this thread


>>And, after all, we use virtual memory nowadays. Doesn't this include one more
>>indirection (done by hardware). Without knowing much about it, I wouldn't be
>>surprized, that hardware time for those indirections is needed more often with
>>the random access style pattern.
>
>You are talking about the TLB.
>
>The memory mapping hardware needs two memory references to compute a real
>address before it can be accessed.  The TLB keeps the most recent N of these
>things around.  If you go wild with random accessing, you will _certainly_
>make memory latency 3x what it should be, because the TLB entries are 100%
>useless.  Of course that is not sensible because 90+ percent of the memory
>references in a chess program are _not_ scattered all over memory.
>

Aha, that's interesting. So memory latency is really the time between switching
the physical address to the bus and getting the data _and_ does not consider
translation from virtual to physical addresses via TLB (Translation Look-aside
buffer)?

So Vincent's benchmark seems not that bad to get a feeling for "worst case"
virtual address latency - which is likely for hashtable reads.

Gerd



This page took 0.95 seconds to execute

Last modified: Thu, 07 Jul 11 08:48:38 -0700

Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.