Computer Chess Club Archives




Subject: Re: Another memory latency test

Author: Keith Evans

Date: 12:23:19 07/17/03

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It will be interesting to find out the discrepancy in the reported latencies.

I remember years ago that DRAM had a tRC of 110 ns, so in theory you could do an
endless stream of random reads and not see a latency worse than 110 ns at the
hardware level. (Excluding the occasional increase due to refresh.)

Of course you could have seen twice that do to heavy loading of DRAM signals
(which meant that you couldn't meet the paper spec), inefficiencies in the
processor or chipset,...


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