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Subject: Re: Another memory latency test

Author: Robert Hyatt

Date: 14:08:41 07/17/03

Go up one level in this thread

On July 17, 2003 at 16:11:33, Gerd Isenberg wrote:

>>Vincent: 256 ns
>>Note, random access is faster than before
>>I get similar numbers for smaller sizes bigger than the cache
>>Summary: There is more, than just an lmbench number. Actually
>>the comment in lmbench source suggests, that they actually
>>wanted to get the random access times.
>>I don't want to argue about defenition of the "real" memory
>>latency. But for chess programs/hash the Vinent type number
>>is the most interesting.
>very interesting Dieter,
>your algorithm confirms roughly Vincent's results!
>I will try it later at home and learn from your source code ;-)
>But there is still the question whether this measured times is memory latency
>per definition - i guess not.

The classic definition of memory latency is the amount of time needed to
do a random read to any specific memory address.  If you blow the TLB, then
you just added another one or two memory accesses which means you are now
doing two or three accesses rather than one.

Calling this "memory latency" is wrong.

I've said this to him before.  Again, the terminology is pretty specific
everywhere I see it.  If you want to define latency to include the MMU
overhead, then the latency becomes variable, depending on the page table
segment table and TLB accesses.

>In worst cases there is more than memory latency (additional TLB-latency and
>some RAM hardware interface latencies) to get data into a register - maybe a
>question of definition.

The TLB problem can easily exceed the cost of reading the data.  In fact,
the PC has a three-level memory map that most systems don't use.  But to do
so adds yet another 120-150ns to latency because you are fetching yet another
memory word.

>Another interesting point is to measure not only the average but the maximum and
>minimum access times (processors performance counter?). Are the accesses  about
>equal, or are there heavy spikes due to some chaotic TLB behaviour?

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