Computer Chess Club Archives




Subject: Re: Another memory latency test

Author: Keith Evans

Date: 16:00:27 07/17/03

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On July 17, 2003 at 18:55:05, Vincent Diepeveen wrote:

>On July 17, 2003 at 18:04:56, Keith Evans wrote:
>>On July 17, 2003 at 17:55:54, Vincent Diepeveen wrote:
>>>On July 17, 2003 at 15:23:19, Keith Evans wrote:
>>>>It will be interesting to find out the discrepancy in the reported latencies.
>>>>I remember years ago that DRAM had a tRC of 110 ns, so in theory you could do an
>>>>endless stream of random reads and not see a latency worse than 110 ns at the
>>>>hardware level. (Excluding the occasional increase due to refresh.)
>>>Are you talking about cray supercomputers or something?
>>Low end graphics chips - this is a concern when you're doing things like drawing
>>vertical lines.
>Is there a chipset and other stuff between RAM and a chip there?

The graphics controller was directly connected to the memory - not one of those
really cheap shared memory setups.

(This was DRAM so we had to use a DLL to get all of the edges to control the
memory so that we could meet all of the memory specs and operate at the maximum
specified rate.)

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