Author: Matthew Hull
Date: 09:26:12 08/07/03
Go up one level in this thread
On August 06, 2003 at 17:30:24, Slater Wold wrote: >I clicked the "Call me now" option, entered my name & number, and 20 seconds >later someone from IBM called me. Cool. > >Of course she couldn't answer my question, but I did get an answer: > >"For high performance computing (HPC) customers, the p690 has an HPC option that >can provide increased memory & I/O bandwidth per processor, resulting in >improved performance and enhanced throughput. This specially configured version >can elevate performance on certain applications by as much as 30% to 45% over >what standard p690 configurations can provide." > >"In the standard p690 each POWER4 chip contains two processing cores that share >an L2 cache. With the p690 HPC option, each chip contains only one processing >core, making the chip's full I/O and memory bandwidth available to the single >processor." > >It's about $4M, in a 32-way configuration. I still wonder though. The PDF you pointed to only talked about SMP interleaving within the MCM. It gave no indication if inter-MCM memory interleaving leaving once again the impression of NUMA. Also, if the CHIP is reduced to one processor core in the HPC configuration, how does that affect the number of CPUs per MCM and does it necessarily improve NUMA latencies? Maybe it only improves MCM performance. MH
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.