Author: Johan de Koning
Date: 23:13:33 08/23/03
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On August 23, 2003 at 09:40:45, Gerd Isenberg wrote: >On August 23, 2003 at 04:21:28, Johan de Koning wrote: > >>On August 23, 2003 at 03:45:09, Johan de Koning wrote: >> >>> ... 1 extra line in main() can >>>easily change the runtime by 1 or 2% (for reasons I haven't fathomed yet). >> >>I mean: I do understand it depends on code alignment. >>I can imagine the instruction pipeline feeds at very high speed from an "open" >>cache line. I can also imagine it is rather complicated to have more than 1 >>cache line "open". But I can't imagine why I get random results. >> >>/**/ for( i = 0; i < top; i++ ) sum += i; >>;;;; more: add, inc, cmp, jl more >> >>This loop usually executes in 2 cycles. But depending on the alignment I get >>somtimes 2.667 or 4 or 4.5 cycles. Isn't that weird?! >> >>... Johan > >Hi Johan, > >Ok, your loop body is about 10 bytes. >If i look to AMD Athlon Processor >x86 Code Optimization Guide TM Page it becomes clearer. >I guess P4 is similar. Thanks, it does indeed make things clearer. Still not 100% though. In the meanwhile I did some thorough testing (using an assembler! :-). It did reveal that 16-byte boundaries are critical, not cache lines. Unfortunately I couldn't reproduce fractional cycles. Maybe I recall them from cache latency tests. If I do manage to see them again I will report ASAP. >Page 49 > >4 Instruction Decoding Optimizations >... > >Overview I do agree with Chris that adapting to a machine on (sub)cycle is not the way to develop a better algortithm. However, I'm currently contemplating a change of data representation. I'd better be ready for the latest and the next generations of CPU and it seems I have some catching up to do. So I find this mighty interesting stuff. <lazy mode> Is this stuff available on-line? Preferrably in plain text format. </lazy mode> ... Johan
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