Author: Robert Hyatt
Date: 16:58:42 09/08/03
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On September 08, 2003 at 19:06:32, Jeremiah Penery wrote: >On September 08, 2003 at 14:53:57, Robert Hyatt wrote: > >>On September 08, 2003 at 14:30:41, Vincent Diepeveen wrote: >> >>>P3 has 512 entries BTB (branch target buffer) >>>K7 has 2048 entries BPT (branch prediction table) >>>opteron/amd64 has 16384. >>> >>>Intel runs behind for complex software. >> >>That is irrelevant (the size). The Intel BTB is _far_ better than >>that on any of the other processors you mentioned. > >I wouldn't bet on that. > >The K6-2 (? -- One, or all, of the K6 series, anyway) had better branch >prediction than any of those processors, including the P4. I'm sure Opteron's >is not worse than P4's. > >I can give tons of references for the K6 data if you'd like. To the best of my knowledge, assuming a program does this: T-NT-NT-T-T, and in that case most always goes T (taken) the next time, the PIV will get it right. If that same program also frequently goes NT-NT-T-NT-T and then almost always goes NT (not taken) then the PIV will get that right too. Each time one of those "patterns" arises, it will hit it dead on. I don't believe the K6 can do that. This algorithm was developed at a University in Texas (I don't recall which) and a paper was published about 2 years ago or so by the people doing the work. It is _very_ good for patterns that are based on a pattern of length 5 or less, and it can handle 32 different such patterns and correctly predict the next branch after any such pattern, which is cute. That reduces the true number of BTB entries, but each BTB entry is much longer and carries much more information (IE each BTB handles all of the possible patterns that have happened for that address previously).
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