Author: Jeremiah Penery
Date: 16:01:05 09/26/03
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On September 26, 2003 at 18:04:04, Uri Blass wrote: >I do not know the future and I admit that I understand nothing about future >computers so I see no reason not to assume that there will not be another >improvement in hardware of having even faster memory(let call it L0 cache) when Your 'L0' cache would be the registers. Opteron, for example, has just over 21Kb of total register space (most is not visible to programmers). >next year computers may have only 128 kbytes L0 cache and 1Mb L1 cache and we >are again in similiar case because now the L1 cache becomes the slow memory. On the P4 and Itanium, L1 access takes only 2 clock cycles. It's practically impossible to get faster than that. I think it takes 3 cycles on Athlons, which is still very fast.
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