Author: Uri Blass
Date: 22:29:31 09/26/03
Go up one level in this thread
On September 26, 2003 at 19:01:05, Jeremiah Penery wrote: >On September 26, 2003 at 18:04:04, Uri Blass wrote: > >>I do not know the future and I admit that I understand nothing about future >>computers so I see no reason not to assume that there will not be another >>improvement in hardware of having even faster memory(let call it L0 cache) when > >Your 'L0' cache would be the registers. Opteron, for example, has just over >21Kb of total register space (most is not visible to programmers). > >>next year computers may have only 128 kbytes L0 cache and 1Mb L1 cache and we >>are again in similiar case because now the L1 cache becomes the slow memory. > >On the P4 and Itanium, L1 access takes only 2 clock cycles. It's practically >impossible to get faster than that. Why? What about memory that you get in time of 0.1 clock cycles? It is 20 times faster. If less than 1 clock cycle is impossible or meaningless because you need to wait to clock cycle then what about doing the clock cycles faster so L1 access takes 20 clock cycles instead of 2 clock cycles and now you suddenly need faster memory. I understand nothing about future hardware technology developement so I only speculate. Uri
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.