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Subject: Re: 64-way Parallel FP Chip

Author: Robert Hyatt

Date: 13:18:28 10/14/03

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On October 14, 2003 at 14:29:36, Gerd Isenberg wrote:

>On October 14, 2003 at 14:15:33, Vincent Diepeveen wrote:
>
>>On October 14, 2003 at 14:13:08, Gerd Isenberg wrote:
>>
>>>On October 14, 2003 at 10:07:10, Ricardo Gibert wrote:
>>>
>>>>
>>>>http://www.wired.com/news/technology/0,1282,60791,00.html
>>>>
>>>>Can this be productively used in a chess program?
>>>
>>>I don't know, simular hardware ressources may be more productive for chess, if
>>>implemented as hyperthreading devices. I guess it's a kind of further
>>>development of SSE and AltiVec technology. With huge register files
>>>(N * 64 * 64|128|256-bit?) and probably SIMD-wise integer instructions
>>>(including popcount?) and fast memory interface, i can imagine that it is
>>>usefull for a lot of nice things, like some eval passes, e.g. a first square
>>>wise and a final scalar product pass. And fill-attack generation, e.g. square
>>>wise in all 16 directions with a specialiced dumb fill routine.
>>>
>>>Gerd
>>
>>this is just floating point arrays.
>
>Aha, well may be a matter of interpretation.
>I havn't seen any instruction set yet.
>
>On the other hand, if float and double arithmetic becomes as fast (or faster) as
>integer, why not use it for eval purposes?
>
>Gerd


Correct.  We did this on the Cray.  FP was very fast there and it frees
up integer registers for addresses and array indices...




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