Author: Vincent Diepeveen
Date: 07:01:44 10/15/03
Go up one level in this thread
On October 15, 2003 at 09:32:10, Robert Hyatt wrote: >On October 14, 2003 at 17:29:18, Vincent Diepeveen wrote: > >>On October 14, 2003 at 16:18:28, Robert Hyatt wrote: >> >>>On October 14, 2003 at 14:29:36, Gerd Isenberg wrote: >>> >>>>On October 14, 2003 at 14:15:33, Vincent Diepeveen wrote: >>>> >>>>>On October 14, 2003 at 14:13:08, Gerd Isenberg wrote: >>>>> >>>>>>On October 14, 2003 at 10:07:10, Ricardo Gibert wrote: >>>>>> >>>>>>> >>>>>>>http://www.wired.com/news/technology/0,1282,60791,00.html >>>>>>> >>>>>>>Can this be productively used in a chess program? >>>>>> >>>>>>I don't know, simular hardware ressources may be more productive for chess, if >>>>>>implemented as hyperthreading devices. I guess it's a kind of further >>>>>>development of SSE and AltiVec technology. With huge register files >>>>>>(N * 64 * 64|128|256-bit?) and probably SIMD-wise integer instructions >>>>>>(including popcount?) and fast memory interface, i can imagine that it is >>>>>>usefull for a lot of nice things, like some eval passes, e.g. a first square >>>>>>wise and a final scalar product pass. And fill-attack generation, e.g. square >>>>>>wise in all 16 directions with a specialiced dumb fill routine. >>>>>> >>>>>>Gerd >>>>> >>>>>this is just floating point arrays. >>>> >>>>Aha, well may be a matter of interpretation. >>>>I havn't seen any instruction set yet. >>>> >>>>On the other hand, if float and double arithmetic becomes as fast (or faster) as >>>>integer, why not use it for eval purposes? >>>> >>>>Gerd >>> >>> >>>Correct. We did this on the Cray. FP was very fast there and it frees >>>up integer registers for addresses and array indices... >> >>That's of course true however at 16 processors of 100Mhz you reached 500k nodes >>a second with cray blitz. >> >>Each Cray processor can issue up to 29 instructions a cycle. > >I have no idea what you are talking about. Each cray processor can issue >_one_ instruction per cycle. > >however, doing vector stuff, in one cycle the machine can do four memory >reads and two memory writes (8 byte words) per processor. It can also do >multiple things in one cycle with vector chaining, but it never issues more >than one instruction per cycle per cpu. > >I don't know what data you are looking at, but it is wrong. > >> >>Crafty at a 1.6Ghz K7 which can issue up to 3 instructions a cycle gets 1 >>million nodes a second. >> >>So something capable of 100M * 16 * 29 = 46.4G instructions a cycle you get 500k >>nps because it is a vector machine Bob cut the crap. If cray would execute 1 instruction a cycle then the processors would be 10 times slower than any other solution. Yet everyone loves crays because they are vector processors which can do up to 29 instructions a cycle. Even a P5/100 would have been faster than a cray because it can do 2 instructions a clock at 100Mhz. You know that a cray can do 29 and i do. So cut this incredible nonsense right here. If you would have vectorized cray blitz correctly it would have run of course faster than 500k nps. More like 5MLN nps at a 16 processor 100Mhz cray. Thank you, Vincent >Again, you make up numbers that have nothing to do with reality. A Cray >can issue one instruction per cycle. The C90 I used for the ICCA DTS >article had a clock cycle time of 4.167 nanoseconds, the standard C90 clock >speed. That is about 250 million instructions per second per processor. With >16 processors, that is 4 billion, not your mythical 46.4 billion. How about >you start writing about things you know something about, and stop making stuff >up about things you don't have a clue about? > >> >>Something capable of 4.8G instructions a cycle you get 1 MLN nps because it is a >>x86 processor. > > >Pure garbage calculations don't convince anybody of anything.
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