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Subject: Re: 64-way Parallel FP Chip

Author: Mridul Muralidharan

Date: 10:43:03 10/15/03

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Hi,

  I think there could be a possible unintentional error in your statements.

If you see evolution of cray :
1) better cycle times (from 12.5ns in the Cray 1 down to 2. 9ns in the SX 3) and
2) higher number of floating point operations initiated per cycle - from 2 flops
cycle in the Cray 1 up to 4 in the Cray C 90 and 16 in the SX 3.

Regards
Mridul

• Re: 64-way Parallel FP Chip Robert Hyatt 13:13:00 10/15/03
  • Re: 64-way Parallel FP Chip Vincent Diepeveen 13:16:47 10/15/03
    • Re: 64-way Parallel FP Chip Robert Hyatt 14:55:18 10/15/03
• Re: 64-way Parallel FP Chip Mridul Muralidharan 11:07:08 10/15/03
  • Re: 64-way Parallel FP Chip Robert Hyatt 19:57:07 10/16/03

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