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Subject: Re: 64-way Parallel FP Chip

Author: Vincent Diepeveen

Date: 13:16:47 10/15/03

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On October 15, 2003 at 16:13:00, Robert Hyatt wrote:

>On October 15, 2003 at 13:43:03, Mridul Muralidharan wrote:
>
>>Hi,
>>
>>  I think there could be a possible unintentional error in your statements.
>>
>>If you see evolution of cray :
>>1) better cycle times (from 12.5ns in the Cray 1 down to 2. 9ns in the SX 3) and
>>2) higher number of floating point operations initiated per cycle - from 2 flops
>>cycle in the Cray 1 up to 4 in the Cray C 90 and 16 in the SX 3.
>>
>>Regards
>>Mridul
>
>
>We are not talking about floating point ops.  We are talking about instructions
>executed.  (issued in Vincent's terminology).  That has _always_ been one
>instruction per cycle, since the first Cray-1, through the T90.  The C90

15 simultaneously at a single C90 processor.

>can do more than four floating point operations per cycle.  A single vector
>operation does two per cycle.  You can chain multiple vector instructions
>together to go beyond that.  The theoretical limit ought to be beyond 8 but
>I will check my C90 manual when I get back in the office...



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