Author: Vincent Lejeune
Date: 11:03:13 10/22/03
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On October 22, 2003 at 13:33:07, Robert Hyatt wrote: >On October 22, 2003 at 11:28:09, Gerd Isenberg wrote: > >>On October 22, 2003 at 03:33:05, Daniel Clausen wrote: >> >>>On October 21, 2003 at 15:29:19, Eugene Nalimov wrote: >>> >>>>On Itanium integer registers are actually 65 bits wide. 64 bits for data and one >>>>NAT (not a thing) bit. >>>> >>>>:-) >>>> >>>>Thanks, >>>>Eugene >>> >>>If there is a way to use this bit for yourself too, I'm sure Gerd will come up >>>with another cool new algorithm! :) >>> >>>Sargon >> >>;-) >> >>I'm really not familar with this very interesting processor architecture. It has >>an integer register file of 128! * 64+NaT. It seems well designed to do a lot of >>parallel fill cycles. >>I guess a set NaT-bit may trigger some exceptions/interrupts if you do some >>operations with uninitialited registers, allowing some lowlevel try-catch like >>control structures (including stack rewind?). >> >>Gerd > > >I suspect it is an integer equivalent of the IEEE NaN concept, so that the >hardware can help you catch using unitialized values. that's what i read wome hours ago at http://www.seas.gwu.edu/~narahari/cs211/materials/lectures/IA64-Roy.pdf page 2 : Architectural Support for Control Speculation • 65th bit (NaT bit) on each GR indicates if an exception has occurred • Special speculative loads that set the NaT bit if a deferrable exception occurs • Special chk.s instruction that checks the NaT bit and branches to recovery, if set • Computational instructions propagate NaTs like IEEE NaN’s • Compare operations propagate “false” when writing predicates But I've not yes one of idea what that mean :)
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