Author: Anthony Cozzie
Date: 07:44:47 12/08/03
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The relevant page here (from Athlon XP manual) is 211 ("Floating Point Execution
Unit"). You can see that the ALU (red) is marked "12-15". Meaning that there
are up to 4 pipeline stages in the floating point units. For example, FADD
takes 4 cycles.
I think you guys need to read up on pipelining 101 a bit. The basic way to
think of this is that the AMD divided the circuitry that computes PAND, PXOR,
etc. into two hunks and put a bunch of flipflops in the middle. So one ALU can
do "the first part" of one PAND and "the second part" of another at the same
time. Latency = 2, Throughput = 1. Note that there is no reason one couldn't
make a 57 stage fully pipelined ALU: Latency = 57, Throughput = 1, but cycle
time is lower.
anthony
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