Author: Gerd Isenberg
Date: 08:47:43 12/08/03
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On December 08, 2003 at 10:44:47, Anthony Cozzie wrote:
>The relevant page here (from Athlon XP manual) is 211 ("Floating Point Execution
>Unit"). You can see that the ALU (red) is marked "12-15". Meaning that there
>are up to 4 pipeline stages in the floating point units. For example, FADD
>takes 4 cycles.
>
>I think you guys need to read up on pipelining 101 a bit. The basic way to
>think of this is that the AMD divided the circuitry that computes PAND, PXOR,
>etc. into two hunks and put a bunch of flipflops in the middle. So one ALU can
>do "the first part" of one PAND and "the second part" of another at the same
>time.
> Latency = 2, Throughput = 1. Note that there is no reason one couldn't
>make a 57 stage fully pipelined ALU: Latency = 57, Throughput = 1, but cycle
>time is lower.
>
>anthony
Thanks Anthony,
i found even more information on Floating-Point Pipeline Stages at Page 220ff.
I missed those information in Athlon-64/Opteron guide :-)
I guess with "parts" you already mean these pipelined execution states 7..15, or
only 12..15?
Does the 2-cycle MMX latency include the sequence of all states from 7..15 (some
skipped), or only 12..15?
What is the maximum MMX throughput of two cycle mmx- direct path (FADD/FMUL)
instructions, with others independently sheduled?
I had the impression to get a max. throughput of < 0.5 but not one.
Gerd
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