Author: Russell Reagan
Date: 20:35:01 02/01/04
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On February 01, 2004 at 23:23:41, Robert Hyatt wrote: >I've never seen a processor with a cache size that isn't a perfect power of two, >as the direct-mapping used for set associative cache depends on using the >rightmost N bits of the address, requiring a power of two size. It's actually the total cache (L1 + L2). AMD's site says it has 128KB of L1 (64KB of data, 64KB of instructions, I think), and 256KB of L2. I guess some have 128KB of L2. All I know is the box my CPU came in said 384KB of cache :)
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