Author: Gerd Isenberg
Date: 12:50:23 02/06/04
Go up one level in this thread
>>With appropriate register files (like Opteron's 16 gp-registers, Itanium or >>SIMD-architectures like MMX/SSE or AltiVec) you may process a lot of independent >>bitboard pattern in parallel (four or even more in one). > >I am more worried about slower processors. The processors you mention >above are all so blazingly fast that it doesn't matter much what I do. >Even my current slow and buggy engine beats me easily on my G4 550MHz, >and on the Opteron it would crush me so badly that I prefer not to think >about it. Optimising for such computers has no point for me; even if I >managed to speed up my engine by a factor of ten I probably wouldn't even >notice the difference. > >I don't target any specific architecture, but want my engine to run >on a variety of processors ranging from StrongARM chips in handhelds >to the PowerPC G5. But of course, the performance of the lower end >of the scale is most important. I need to choose my data structures >in such a way that they are efficient on 32-bit computers with very >limited memory. Do you think bitboards are still worth a try, or >should I continue to use a simpler architecture? Depending on how limited memory is, may be rotated with compact lookup tables, but no fillalgos. Some cheap pawn bitboards... What about working on two concurrent approaches ;-) Palm and G5 with AltiVec? > >>You already noticed Steffan Westcott's "Bitboard algorithm design principles"? > >Yes, I've seen them. Thanks for your advice! :-) > >Tord
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