Author: Gerd Isenberg
Date: 11:48:43 02/17/04
Go up one level in this thread
On February 17, 2004 at 14:02:01, Robert Hyatt wrote: >On February 17, 2004 at 13:48:16, Mark Young wrote: > >>Hydra >>8 x 2.8 Xeon & 8 FPGA Cards >> >>Total games 47 >>Stored results 47 >>White 24 >>Wins 19 >>Draws 16 >>Losses 12 >> >>Results 27/47 = 57.4% >>Opponents Elo 2604 >>N Opponents 31 >> >>Rating 2634 >> >>I see nothing in the results or games to suggest at this time. That Hydra is the >>end all, be all future of computer chess. >> >>The last game I saw Hydra playing Shredder 8 on a P600 and down a pawn when >>Hydra logged off. TC was 15 10. >> >>Dispite the hype... Hydra is not exactly blowing the top PC programs out of the >>water even on much slower hardware. If the results are correct on playchess.com >>for Hydra. > >You have to learn that hyperbole follows any new project. It is fast, and it >plays pretty well. But it isn't _that_ good. IE It is not the second-coming of >deep blue or some such nonsense. I did a few runs on an 8-way opteron two weeks >ago and saw speeds that were around 16-17M nodes per second. Hydra's speed can >already be reached by existing hardware, and without the issues of no hash in >hardware, its speeds can be beaten with existing machines. > >IE the last version of Belle was first seen in 1980. By 1983 Cray Blitz was >out-searching it. And we continued to get faster every year while Belle was >stuck at the hardware speed it was built around. > >DB's 200M nodes per second average was incredible in 1997. I've searched 10% of >that speed already and there are boxes around that will go maybe 4x faster than >that. So today, it is possible to search about 1/2 as fast as deep blue, but >with their hardware non-hashing problem, we might be faster today. > >Time marches on, hardware designs tend to be "flash in the pan" things, >brilliant today, not so fast tomorrow, slow next year... but even FPGAs became faster and more sophisticated the next years. It's probably a bit more flexible/portable architecture than former solutions. PCI(X)-bus is the bottleneck, so there is a tradeoff between PCI-bus bandwith/latency and number of hashless FPGA-plies. May be it's even possible in the future to do four(+quiescence) FPGA-plies with appropriate branching factor and driving PCIX on the limit. Chrilly already implemented killer heuristics... I believe they will domitate the scene for a few years. But of course i may be wrong ;-)
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