Author: Robert Hyatt
Date: 06:52:53 02/21/04
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On February 21, 2004 at 02:02:32, Mathieu Pagé wrote: >Hi, > > Sorry for the out topic post but i searched for this on google and news groups >for some time now and I know some of you can answer me as it is something we >have to deal with while creating chess engines. > > Tonight I have change my type PIECE from an enum to a typedef chat PIECE with >some #defines for the differents pieces and I got a speed up of 37 % of my >engine while doing perft test. > > I thin that this is due to a better use of the cpu's cache. I was wondering >what is the ratio betwen cache and RAM latency. Is it as big as RAM VS HD >latency ? > >Mathieu P. It is not as big as ram to disk, but it can be substantial. To read a word from memory typically requires 125ns. Reading from cache can be as little as one cycle, which could be 1/3ns on a 3ghz box. L1 is fastest, L2 has a longer delay, but either is _way_ faster than main memory. Figure 100:1 as a good first approximation. Taking advantage of cache is _the_ main optimization idea for modern microprocessors.
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