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Subject: Re: Dual core opterons to be pin for pin compatible with single core uni

Author: Dan Andersson

Date: 15:30:00 04/29/04

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 A core usually means a full CPU including L1 cache. Depending on the overall
design of cache, inclusive or exclusive, L2 and hypothetical L3 cache will
either be shared or not.

MvH Dan Andersson



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