Author: Gerd Isenberg
Date: 11:23:33 06/02/04
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On June 02, 2004 at 10:47:42, Gerd Isenberg wrote: >On June 02, 2004 at 09:14:38, Gerd Isenberg wrote: > >>One more note ... >> >>The same optimization occurs with an int-array, if one is aware of the q-value >>range, eg. if q values are in the range from 0..15 it is only necessary to shift >>by four. Considering OOE and register renaming, could one beat that with >>assembly? > >Ok, your initial rcl-one is only 48 bytes versus 98 of the C-Version. >It is slightly faster on a P4 2GHz, but i fear not on AMD, i will try later. >Somthing like 11.2ns versus 11.8ns. Oups i was wrong with my AMD xp 2.8+. Even 7.2ns versus 9.8ns in favor for the asm version including some offset of about 1.5 ns, roughly valuated by a dumb loop test. Ok, code size of this loop matters more than i though. The ipc is obviously better for the C-version. Gerd
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