Author: Joshua Shriver
Date: 21:18:46 06/04/04
Go up one level in this thread
> >The architecture is X86. That means your mov eax, mem stuff will work just >fine, except that it gets extended on the opteron (and eventual intel X86-64 >as well) so that eax becomes rax for 64 bit registers, and then you get the new >r8-r15 extra 8 registers that AMD added. > >I found it trivial to program, assuming you know X86 already. change the >register names, and use the extra 8 that are not there in normal X86 and that's >enough to get you started... At my core I'm an assembly programmer. Just makes more sense to me... while it has proven to be an economical disadvantage in the days of VB programmers I absolutely adore low-level programming and I have a true respect for the architecture. Didnt know that Opterons introduced more registers.. excuse me but *drool* register and L1 cache is the way to go. Know if AMD released any .pdf or whatever docs giving an arch document as Intel does with their line? I'd love to get some low-level Opteron spec docs. I am not the greatest programmer, but I still have asperations for writing a great Chess engine, and hope that multiple assembly cores let alone great C algorithm backends will prove to be beneficiial. I've been working off and on on writing an PPC assembly based core for crafty for a while now. I just hope I can create something worthy that you can incorporate in your code eventually. Anyway thanks for the input it's greatly appreciated sir.. it's always and honor talking with you. Sincerely, Joshua Shriver
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