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Subject: Re: Processor's

Author: Eugene Nalimov

Date: 16:13:44 06/17/04

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On June 17, 2004 at 18:44:24, Vincent Diepeveen wrote:

>[...]
>
>It is not wrong. Itanium2 does not store its weakest point (instructions)
>in the L2 cache but the L3 cache.
>

Wrong. See "Intel Itanium 2 Processor Reference Manual For Software Development
and Optimization" once again.

Table 6-4 explicitly says that L2 to L1I latency is 7 cycles.
Section 6.7 explains "Second-Level *Unified* Cache". (emphasis mine)
Section 6.7.6 describes L2 Instruction Prefetch FIFO (IPF) and explains how IPF
hanles L2 *hits* and L2 misses. (emphasis mine)

>[... lot of meaningless computations and arguments based on the wrong assumptions deleted]

Thanks,
Eugene

• Re: Processor's Vincent Diepeveen 16:45:53 06/17/04
  • Re: Processor's Eugene Nalimov 17:21:34 06/17/04
    • Re: Processor's Vincent Diepeveen 03:26:47 06/18/04

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