Author: Vincent Diepeveen
Date: 03:26:47 06/18/04
Go up one level in this thread
On June 17, 2004 at 20:21:34, Eugene Nalimov wrote: So clearly *that* documents are not representing entire truth, because in official meeting presenting a vaste supercomputer, the intel strategic marketing manager used other data. In short i conclude that you speak again about sequential access times. As usual the random access times aren't mentionned. This is also the case with P4. Anyway the itanium2 processor is unworkable anyway for a single person. Only entire compiler teams can get a program X work at it. The instruction cache is too much of a problem to keep filled otherwise. The opteron simply wins it based upon its Level caches which are way faster. 128KB + 1MB And it's *not* a dsp processor unlike itanium2.
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.