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Subject: Re: Correction hydra hardware

Author: Robert Hyatt

Date: 22:12:37 02/01/05

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On February 02, 2005 at 00:03:26, Matthew Hull wrote:

>
>>>>
>>>>Quote on:
>>>>------------------------------------------
>>>>
>>>>It's 4 nodes.
>>>>
>>>>1 node = 8 processor Xeon.
>>>>------------------------------------------
>>>>quote off
>>>>
>>>>"one node = 8 processor xeon".  That is _clearly_ SMP.  And _that_ is the box I
>>>>was talking about.  I've run on more than one of them.  For chess they are bad,
>>>>running 2 copies of crafty produces 2x NPS of one copy.  Running 4 copies
>>>>produces nearly 4x the NPS of one copy.  Running 8 copes produces barely 6x the
>>>>1 copy speed.
>>>
>>>
>>>Would this be considered a NUMA relationship, between the two 4-way nodes.  Does
>>>your NUMA crafty handle this better than your older SMP-only crafty?
>>>
>>
>>
>>wasn't numa.  Used the Intel "Fusion" chipset to tie two 4-way processor groups
>>together to provide a total of 8, but there was a bottleneck.  It was one of
>>those "let's see what it will do" sort of things.  Big L2 cache processors could
>>provide good performance if memory requirements were limited.
>>I'll take a NUMA opteron system any day.
>
>
>I see now.
>
>What then was the issue with the dual Athlons?  IIRC, the memory was not
>interleaved, so SMP crafty did not do as well on those as on dual Xeon.  Did
>your NUMA changes help with dual Athlons?
>
>Thanks,
>

They used MOESI cache coherency.  Intel prior to the PIV xeon used MESI.  MOESI
uses a cache-to-cache communication link that will let one cache share a line of
modified data with the other without going thru memory as a MESI cache does.
Problem is that it is possible to swamp this channel, which is what I was doing.
 By reorganizing shared but not modified data and moving it away from
shared/modified data (like spin locks for example) that cache update traffic was
reduced significantly...


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