Author: Robert Hyatt
Date: 08:57:54 02/03/05
Go up one level in this thread
On February 03, 2005 at 11:17:31, Vincent Diepeveen wrote: >On February 02, 2005 at 11:54:46, Robert Hyatt wrote: > >>On February 02, 2005 at 09:53:03, Vincent Diepeveen wrote: >> >>>On February 01, 2005 at 21:51:19, Robert Hyatt wrote: >>> >>>>On February 01, 2005 at 17:19:26, Vincent Diepeveen wrote: >>>> >>>>>On February 01, 2005 at 16:28:22, Robert Hyatt wrote: >>>>> >>>>>Still didn't read the subject title? >>>>> >>>>>[snip] >>>>> >>>>>>Because a cluster can't offer 1/100th the total memory bandwidth of a big Cray >>>>>>vector box. >>>>> >>>>>Actually todays clusters deliver a factor 1000 more or so. >>>>> >>>>>Total bandwidth a cluster can deliver is measured nowadays in Terabytes per >>>>>second, with Cray it was measured in gigabytes per second. >>>> >>>>Let's see. The last Cray I ran on with a chess program was a T932. Processor >>>>could read 4 words and write two words per cycle, cycle time was 2ns. So 6 >>>>words, 48 bytes per cycle, x 500M cycles per second is about 2.5 gigabytes per >>>>second, x 32 processors is getting dangerously close to 100 gigabytes per >>> >>>Bandwidth a cpu at the old MIPS was 3.2 GB/s from memory (origin3000 series) >>>and bandwidth at altix3000 using network4 a cpu is 8.2 gigabyte per second from >>>memory. >>> >>>So what Cray streamed there was impressive for its days, but it delivered to >>>just a few cpu's, that was the entire main problem. This for massive power >>>consumption. >>> >>>What we speak of now is that you get effectively the same bandwidth from memory >>>to each cpu now, but systems go up to 130000+ processors. >>> >>>>second. A "cluster" can have more theoretical bandwidth, but rarely as much >>>>_real_ bandwidth. This is on a shared memory machine that can do real codes >>>>quite well. >>> >>>>> >>>>>Note it's the same network that gets used for huge Cray T3E's, but a newer and >>>>>bigger version, that's all. >>>> >>>>T3E isn't a vector computer. >>> >>>The processor used (alpha) was out of order, yet achieves the same main >>>objective, that's executing more than 1 instruction a cycle effectively. >>> >>>Itanium2 is objectively seen is a vector processor as it executes 2 bundles at >>>once. Though they call that IPF nowadays. >> >>That's not a vector architecture. A vector machine executes _one_ instruction >>and produces a large number of results. For example, current cray vector boxes >>can produce 128 results by executing a single instruction. That is why MIPS was >>dropped and FLOPS became the measure for high-performance computing. > >IPF executes 2 bundles per cycle. > >1 bundle = 3 instructions in IPF > >You can see that as a vector. Maybe _you_ can see that as a vector. No person famil
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