Author: Steven Edwards
Date: 02:13:05 05/10/05
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On May 09, 2005 at 10:01:53, Robert Hyatt wrote: >On May 09, 2005 at 07:48:51, Steven Edwards wrote: > >>The PowerPC architecture has an instruction for counting the leading zero bits >>in a word. This is either a 32 bit or a 64 bit operation depening on the CPU >>mdel and mode in use. Naturally, this instruction can be helpful for optimizing >>the FirstSq and NextSq functions. Unfortunately, there is no PowerPC >>instruction for bit counting. >Some non-standard Crafty versions uses the PPC stuff thru an intrinsic. The >normal versions do not, but someone wrote the changes for their PPC box. > >Yes, a0 -> MSB, because the PPC uses the same approach as the Cray, which rather >than finding the first one bit, counts leading zero bits instead. I'm going to >change this one day to get rid of the 63-X stuff necessary because of the way >the X86 BSF/BSR count bits from the other end... I''ve run a number of tests and have come to the conclusion that it doesn't make much difference having NextSq instructions with small immediate operands. In other words, it looks like any reasonable implementation that avoids table lookup is going to give about the same performance. As you know, just about every NextSq call is part of a tight loop that fits into L1 cache, so there's little or no fetch/decode penalty for immediate mode operand instructions (assuming that appropriate ones are available). In fact, there may be a bonus in some cases (e.ge, PowerPC RISC/many registers) as I've seen. Things could be different in x86 land. I still wonder about the lack of a bit count instruction in the PowerPC. Back in my Control Data assembly language days I used the CXi Xj opcode a number of times, and I'm familiar with the story about the US National Security Administration telling Seymour Cray that one was needed (and why). The opcode was useful, but admittedly rather out of place on what was essentially a giant floating point calculator.
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