Author: Gerd Isenberg
Date: 14:40:38 08/27/05
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<snip> >>>Are you saying Gerd that: >>> >>> mov EAX, mem32 is faster than mov AL,mem8 ? >> >>Yes, slightly - accordind to the optimization manual three (not 1!) cycles >>instead of four (both in 32-bit as well in 64-bit mode): > >Ok. > > >>MOV reg8, mem8 8Ah mm-xxx-xxx DirectPath 4 >>MOV reg16, mem16 8Bh mm-xxx-xxx DirectPath 4 >>MOV reg32/64, mem32/64 8Bh mm-xxx-xxx DirectPath 3 > >So why are chess engines still using 8-bit boards and tables? > >He he he.... > hmm... i have to relativate it a bit, also the answer to Mridul as well. Most simple arithmetical and bitwise instuctions have four cycles for both 8-bit and 16/32/64-bit instructions. ADD reg8, mem8 02h mm-xxx-xxx DirectPath 4 ADD reg16/32/64, mem16/32/64 03h mm-xxx-xxx DirectPath 4 CMP reg8, mem8 3Ah mm-xxx-xxx DirectPath 4 CMP reg16/32/64, mem16/32/64 3Bh mm-xxx-xxx DirectPath 4 But see 2.23 32-Bit Integral Data Types in the manual... Alignment and stalling issues are probably more important. <snip> >>>>Also, avoid the shorter but redundant EAX-Move encoding: >>>> >>>>MOV AX/EAX/RAX, mem16/32/64 A1h DirectPath 4/3/3 >>> >>>Right, never us it. >> >>Nope, A1h mem16/32/64 move has the same latency (4/3/3) than the one byte longer >>8Bh opcode for all gp-registers. Sorry for confusing. Anyway it is usually the >>choice of the assembler or compiler, unless you code directly in machine >>language ;-) > >So it has been fixed after all, not that I see much practical use. The old 8080 accu. Still a privileged register with some shorter opcodes here and there. Cheers, Gerd > >Thanks Gerd. > >Ed
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