Author: Dezhi Zhao
Date: 11:54:53 09/28/05
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On September 28, 2005 at 14:07:04, Gerd Isenberg wrote: >>>>You said it! They keep this bad tradition. The problem is shift operations are >>>>slow on P4 class processors. Shift is still slow on x86-64, right? >>> >>>No, best case on x86-64, direct path, 1 cycle latency with 8/16/32/64-bit >>>registers, regardless of the number of immediate or variable (cl) shifts. >>>And of course a huge win for 64-bit shifts! >> >>1 cycle for qword shift on AMD CPU?! This is a really good surprise to me! >>How about the shift operations on Intel x64? I don't think a P4 with x64 >>extension can do one cycle shift on an integer of any size. > > >P4 has four cycles latency for shifts (1 cycle Throughput), no idea about the >x86-64 clone, i guess Centrino (based on PIII) is better. > >SAL/SAR/SHL/SHR 4 1 Yes, P-M is much faster than P4 on shift operations. Just looked some x86-64 asm output from VS2005. It seems to me the 64 bit code still leaves some room to be improved. I'm going to post the test code and asm output after I take a closer look at it tonight.
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