Author: Gerd Isenberg
Date: 13:23:22 11/08/05
Go up one level in this thread
On November 08, 2005 at 15:26:45, Vincent Diepeveen wrote:
>On November 08, 2005 at 13:17:42, Yar wrote:
>
>>Hello,
>>
>>Here is review (total 14 pages) of upcoming Intel's Xeon 5000 (Dempsey). Sorry
>>its only in german. It seems its faster then Opeteron 280.
>>http://www.tecchannel.de/server/hardware/432957/
>>
>>With best regards,
>>
>>Yar
>
>It should be a fast cpu that Dempsey. However that Xeon will be there januari
>2007 or so and it will have a price of i guess around 5000 euro a cpu in the
>quad version, if you can get it for that, as you'll have to buy probably
>1000 at a time to get them for around 4500 dollar a piece.
>
>So effectively a quad xeon dual core will be januari 2007 around $40k.
>
>By that time of course a quad opteron quad core is nearly 2 times faster
>and exactly 2 times cheaper.
>
>Please note that it's not sure whether the IPC from the intel pentium-m at such
>high clockspeeds and dual core will be better than from AMD. I'm counting at it
>that it will be a lot slower, because in order to clock pentium-m higher, intel
>will need to make the pipeline longer and will probably move from a 2 cycle L1
>to a 3 cycle L1. In which case the processor is similar to the opteron from
>chessprogramming viewpoint.
>
>Of course the Xeons have bigger L2 or even L3 caches on chip than AMD. That's
>nice for certain applications that are in benchmarks, but in reallife it's not a
>huge advantage.
>
>A few MB's is plenty for computerchess at the moment.
>
>On the other hand, could you tell me whether this Xeon has an on die memory
>controller or doesn't it have one?
>
>Because *that* matters a lot. Hashtables is a matter of TLB trashing memory
>latencies to a big hashtable. With 64 bits cpu's and the clock that keeps
>ticking, the RAM sizes will increase too, meaning that the latencies you lose to
>TLB trashing (transpositiontable , eval table, not so much pawntable as that'll
>be in L2 cache for majority of accesses) are significant.
>
>If intel plans to do that via some sort of chipset off chip, then that is a huge
>drawback of this Xeon cpu for databases and chess. At database benchmarks, using
>some small database they can get away with a big L2/L3 then, but in real life
>there is no escape there. It's just dead slow.
>
>So i do look forward to pentium-m, but the price at which intel usually sells
>good cpu's doesn't mean that we will see more quads online.
>
>Vincent
Yes, memory latency seems worse.
OTOH intel has more than two times better bandwith using 128-bit SSE2/3
load/store instructions, which is of course not so important for cumputer chess.
Cache/Speicher: 128-Bit-Transfer
Bandwidth in MByte/s
Dempsey Paxville Opteron 280
L1 47340 41444 18360
L2 24928 22105 9448
Memory 3606 4127 3316
Also general SSE-performance is much better for the future intels.
Hopefully some motivation for amd to work on 128-bit alus ;-)
Gerd
This page took 0 seconds to execute
Last modified: Thu, 15 Apr 21 08:11:13 -0700
Current Computer Chess Club Forums at Talkchess. This site by Sean Mintz.