Author: Vincent Diepeveen
Date: 12:51:01 11/23/05
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On November 21, 2005 at 20:00:24, Eugene Nalimov wrote: >On November 21, 2005 at 18:10:54, Dieter Buerssner wrote: > >>[...] >>I guess, you mean this as a substitution for >> if (depth < 0) >> fm = fm1; >> else >> fm = fm2; >> >>I am surprised, that compilers are not able to do this themselves. I > >I several times tried to modify Visual C to recognize additional cases where we >should emit conditional moves (last time was probably a year ago for >x64-targeting compiler). Every time I could demonstrate win on a small >artificial test case, but every large real world program either showed no gain >or slowed down. At *which* processor was it slower. AMD or EM64T? AMD has quite a big L1 cache and has instruction cache in L2 if i understand correctly. That should make larger code sizes no problem. So i assume intel EM64T became slower and as a result of that it was abandonned? Vincent >I suspect there are several reasons for this: >* branch predictors are good, and majority of branches can be correctly >predicted >* CMOV is long instruction; short branch is shorter, so program with less CMOVs >fits better into cache >* there is no 8-bit form of CMOV >* CMOV has no "CMOV reg, immediate" form; if you need it you first have to load >immediate into register, this executing more instructions and increasing >register pressure -- serious problem on x86 >* for invalid address "CMOV reg, memory" will give you access violation even if >condition is false. > >Thanks, >Eugene
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