Author: Bo Persson
Date: 09:08:28 12/13/05
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On December 12, 2005 at 17:01:35, Uri Blass wrote: >On December 12, 2005 at 14:38:48, Chrilly Donninger wrote: > > > Some constructs are in contrast on the FPGA >>almost impossible. E.g. the size of RAM-Tables is fixed to 4 (old Virtex-I) and >>now 18-KBits (Bits not Bytes). One has to split up everything that it fits into >>these small tables. And one has also to restrict the possible values. A typical >>Hydra-Tables as 12 Bits Input and 4 Bits output or just 16 different values. >>One has also to avoid any sequential thinking. E.g. I calculate first the pawn >>structure and the rest of the eval depends on this. In Hardware this runs all >>parallel. If one makes it sequential, one has already lost. > >I guess that you mean that you lose speed but the question is if speed is >everything and if it is not possible that it is better to have more correct >evaluation by sequential thinking and be slower. > The thing with custom hardware is that you can do some things *both* correct and fast, at the same time. The "trick" is to take advantage of these strenghts, and try to avoid operations that have high cost (meaning not being fast, or using a large part of the chip). We have the same problem in software, it is just that the costs are different. Some things that are relatively expensive in software, like counting bits, can be cheap if you can build an adder. One problem for hardware designs, is that it is limited in the number of operations that can be fit on a chip. In software you can add millions of logic operations at a very low cost - just write some more code. And even though we softies cannot build custom instructions, we can buy standard chips with GHz clocks. Bo Persson
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