Author: Gian-Carlo Pascutto
Date: 10:22:26 12/27/05
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On December 27, 2005 at 12:37:12, Zappa wrote: >I really doubt it. Hydra on some sort of FPGA emulator would search about 4 >nodes per second. > >I used to run simplescalar which simulates an out-of-order core. That slowed >things down by a factor of 1000. Simulating all the gates and wires in the >hydra HDL would be far worse. There is no need to do that unless it's actually programmed at the gate level, which would be an insane thing to do. If it's VHDL or Verilog then you can do a behavioral simulation, ignore all hardware aspects, and the speed would be about that of a crappy interpreter. It would still massively suck, of course. -- GCP
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