Author: h.g.muller
Date: 13:11:27 02/07/06
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On February 07, 2006 at 13:11:55, Robert Hyatt wrote: >Also on the PC this is a variable latency problem, since the first word you ask >for might be the last word of a cache line, in which case the next word will >have another large delay built in.. The cray doesn't do "cache lines" for >vector operations... I know, the Cray was a great machine (even though current PCs can beat the old Y/MP by a factor 10, if you program them carefully). But you underestimate the Pentium and its brethren: they load a cache line in the smart (or at least: non-dumb) order, starting with the word that is first needed (at the address where the original cache miss occured). Even if it is the last word in the cache line. For a 4-word burst due to a miss on address 12 the order would be 12,8,4,0. The address bits toggle in the usual binary counting order, but start out at a funny value (probably by xoring the requested address with a normal counter internally).
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