Author: h.g.muller
Date: 05:41:51 02/28/06
Go up one level in this thread
>I don't know the details about Intel processor history, but I do know that the >higher efficiency per clock cycle (and something about a shorter execution line) >is the usual way to explain AMD processors current superiority in most >applications, not least chess engines. I have understood that Intel is looking >to catch up in that aspect with the new Intel Core, which indeed will generally >run in lower frequencies that the Pentium chips. > >Kind regards, >Dagh nielsen Actually Intel hailed the "do-less-per-clock-cycle" philosophy as the way of the future at the introduction of the Pentium IV. The idea was that the higher clock rate that could be achieved this way would offset the fact that more cycles were needed to complete execution of an instruction, so that latency would stay about the same in time units (rather than clocks). The advantage that you could start more instructions per second, since they can be shoved into the pipe line at clock speed, would then remain. This would be especially good for programs with a predictable branch pattern (fixed-length loops and almost no conditional code, like image processing). For unpredictable branchess it is the latency, rather than the throughput, that counts: the latency determines how long it takes before you discover the prediction error, and thus how many seconds worth of pipe line have to be flushed. So in programs littered wth unpredictable branches, (like chess engines!), the benifit is nil. Even worse, because the isolation gates between the various pipe-line stages add some time to the pipe-line transit, you're off worse even in terms of real time. Intel pulled off this trick (i.e. do less per clock) once before in a quite successful way, when introducing the P6 core in the Pentium Pro. Its pipe line was about 50% longer than that of the original Pentium, translating to higher clock speeds at the same chip technology. The disadvantages of the increased latency were largely offset then by the introduction of the CMOV instruction (allowing elimination of many unpredictable branches) and the out-of-order execution (avoiding data-forwarding stalls that the larger latency would cause on existing code). But when P-4 was introduced all that allready existed, and the disadvantages of the longer pipe line became painfully clear. The P6 was far ahead of its time, it was introduced almost simultaneously with the ordinary Pentium, and represented a revolution in CPU design. This has made Intel lazy in developing truly new stuff, except P-4 all their CPUs since Pentium Pro, including P-II, Celeron, P-III, Celeron-2, were only small variations on the P6 core, adding a few instructions to the decoder that could be performed by using existing execution hardware in a more efficient way, and fiddling with the L2 cache. Even Pentium M seems to be an upgraded P6, with the bus interface replaced by that of P-4. (The fast bus was the only thing the P-4 had going for it in the early tests, without the fast RAM access it would have been a complete disaster...) AMD had some catching up to do, and while Intel was idling the developed the K7. This K7 was really the next generation to the P6, it was based on the same degree of pipe-lining as the P6, but it had more of everything: 3 integer execute units rather than 2, 3 clever x386 instruction decoders rather than 1 clever and 2 dumb decoders, 3 addres generation units rather than 2, 2 load/store paths to the L1 cache rather than 1, an FPU that could do add and multply in the same clock,... Although the limit of 3 micro-ops per clock was the same in K7 and P6, the wider micro-ops of K7, which combined load/store and calculation operations in one micro-op (what Intel now calls micro-op fusion in Pentium M) caused the same code to be translated in only half the number of micro-ops. These are the reasons that the AMD chips perform so much better than the Intel P6-based stuff. They simply have more hardware on board.
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