Author: Robert Hyatt
Date: 04:42:11 05/18/99
Go up one level in this thread
On May 17, 1999 at 22:37:30, James B. Shearer wrote: >On May 17, 1999 at 09:28:31, Robert Hyatt wrote: > >>On May 17, 1999 at 00:36:39, James B. Shearer wrote: >> >>>On May 14, 1999 at 09:52:14, Robert Hyatt wrote: >>> >>>>On May 14, 1999 at 01:38:11, Gregor Overney wrote: >>> >>> <snip> >>> >>>>> >>>>>2) You still need to write the correct algorithms to make this chip work. And >>>>>those algorithms are pretty complex (see evaluation functions etc.) >>>>> >>>> >>>>But it has _already_ been done. All that is left is to use the "new" fab >>>>process to increase density and clock speed.. DB's chess chips only ran at >>>>20-24 megahertz. running that up to 16x faster seems quite easy with todays >>>>silicon capabilities as that would still be a modest < 400mhz processor. >>> >>> This assumes: >>>1) Hsu's startup has the right to use the IBM deep blue code. >> >>He's already publicly stated that he is doing this, so I would assume that >>permission has already been granted? > > I have not seen any such statement. > Then pick up the current issue of IEEE Micor and you will. :) >> >>>2) The IBM deep blue code (written for the big endian power chips) can be >>>trivially ported to the (little endian) Intel chips used in PCs. >>> I would doubt both of these assumptions. >>> James B. Shearer >> >>(2) is a non-issue. IE 'crafty' is much more 'endian' aware than DB, yet it >>runs on big-endian and little-endian machines with no problems at all. The >>PCI interface could 'correct' the endian-order of the data without the chip >>ever knowing... > > (2) might be a non-issue if the deep blue code was carefully written to >be endian independent. Is crafty naturally endian independent or carefully >written (and tested) to be endian independent? There are often major problems >in porting code to other endian machines if this was not considered and designed >for from the start. > James B. Shearer crafty is endian-sensitive, and has been specifically written to work with big-endian _and_ little-endian architectures. In the case of DB processors, since they sit outside the PC processor, and behind a PCI interface, the PCI interface itself can easily handle the endian issue if they have one.
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