Author: Andrew Slough
Date: 12:12:28 06/12/99
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On June 11, 1999 at 11:38:31, HungryGoldfish wrote: >We all want what is best for the chess programs we love. Just as we wish to >give our children nutritious foods, we wish to give our programs fast processors >and lots of RAM. > >Is a program running on a 400 MHz chip with 512K backside significantly fater >than a 400 MHz chip with 1.024K backside catch? > >How would the 400 MHz chip with 512K compare to a 400 HMz chip without any cache >at all? > >And just in case it matters, my program of choice is HIARCS. The problem for chess programs is that the hash tables generally thrash the L2 (backside) cache. Because good hashing algorithms will get pseudo-random access into the hash table, the hit rate on the L2 cache will not be very high. The size of the L1 cache is much more important because all processors like Pentium/K6 have two caches, split into instruction cache and data cache. In this way your hash tables can't kick out your program code. Rebel sees slightly better performance for K6 than PII/III per Mhz, and I'm pretty convinced it's because the K6's L1 cache is twice the size. If you have a really large program though, then that won't make so much of a difference, and the PII's faster L2 cache will give a bigger performance boost. Andy
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