Author: Robert Hyatt
Date: 13:14:00 06/13/99
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On June 13, 1999 at 15:18:29, Ernst Walet wrote: >> >>actually it is... but it is called the PII/xeon, although I bet that >>fritz/junior are on PIII/xeon's instead, which are better once compilers >>start using all the new instructions.. >> >> >> > >Actually it isn't. Ok ok, the core is, but the level 2 cache isn't in speed and >can be larger in size. So to mention it in the line of the Pii used by Fritz >and Junior is not completely punctual. Blame the brain-dead people at Intel that name the things. I have four of 'em in my box and on each module they say "Intel Pentium II Xeon". And I have tested on a box that said "Intel Pentium III Xeon". The "xeon" is the trigger to know that the L2 cache is at core cpu speed. Without that word, you get a L2 cache at 1/2 core speed and only in 512K, while the xeon can be had in 512K, 1024K and 2048K L2 sizes... But Intel has always had trouble naming processors. IE 486/33 with a 33mhz bus speed, 486/66 DX2, running internally at 2x the bus speed, and then the 486/100 DX4 running at _3X_ the bus speed. :) where the "DX" was their 'clock multiplier' nomenclature...
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